The present invention relates to an electrostatic discharge (ESD) protection scheme for integrated circuit devices and, more particularly to an ESD protection scheme with improved turn-on performance.
As is explained in detail by S. Wolf in Silicon Processing for the VLSI Era, Volume 2, 1990, the input signals to a metal-oxide-silicon integrated circuit (MOS IC) are fed to the gates of MOS transistors within the integrated circuit. If the voltage applied to the gate insulator is excessive, the gate oxide will break down. The dielectric breakdown strength of SiO2 is approximately 8.times.10.sup.6 V/cm; thus, most gate oxides will not tolerate voltages greater than 12-15 V without breaking down. Although this is well in excess of the normal operating voltages of 5 V integrated circuits, voltages higher than this may be impressed upon the circuit integrated circuit pads as a result of human-operator or mechanical handling operations.
The main source of such high voltages is triboelectricity (electricity caused when two materials are rubbed together). A person can develop very high static voltage (a few hundred to a few thousand volts) simply by walking across a room or by removing an integrated circuit from its plastic package. If such a high voltage is accidently applied to the pins of an IC package, the resulting electrostatic discharge (ESD) can cause breakdown of the respective gate oxides to which it is applied. The breakdown event may cause sufficient damage to produce immediate destruction of the device, or it may weaken the oxide enough that it will fail early in the operating life of the device.
It has become a widely held practice to provide ESD protection circuits for all the integrated circuit pads or pins of MOS ICs. The need for such circuits is particularly acute for VLSI devices in such high-noise environments as personal computers, automobiles, and manufacturing control systems. These protective circuits, normally placed between the input and output pads on a chip and the transistor gates to which the pads are connected, are designed to begin conducting or to undergo breakdown when the integrated circuit pads are at a relatively high electrical potential, thereby providing an electrical path to ground or the power supply rail. Since the breakdown mechanism is designed to be nondestructive, the circuits provide a normally open path that closes only when a high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected.
Unfortunately, many of the existing ESD protection schemes do not provide a sufficiently low threshold turn-on voltage for the associated integrated circuit or are prohibitively complex and expensive to manufacture. Accordingly, there is a continuing need for ESD protection schemes that provide a sufficiently low threshold turn on voltage while doing so with a semiconductor structure that is reliable and relatively inexpensive to manufacture.